Integrated Semiconductor Design Park (ISDP)
Design-led, capital-prudent — secure chip-design infrastructure, GCC attraction and fabless incubation.
Functional Zones
Design and EDA Commons with secure project rooms, K-SDC/K-SC access, HPC and PDK/IP governance · Plug-and-play suites for semiconductor GCCs, design houses, EDA/IP vendors and anchor R&D tenants · Fabless startup and MPW/tape-out accelerator linked to K-FSA, SICC, Maker Village 2.0 and CoE IIoT Sensors 2.0 · Talent and competence zone with VLSI classrooms and certification labs · Shared product-engineering, demonstration, investor, IP/legal and programme-management facilities · Green, resilient and secure common infrastructure.
Year-1 Focus
Complete land allocation, master planning, DPR/statutory packages, site enabling works, trunk utilities and initial Design Commons fit-out within a ₹16.75 Crore allocation.
Expected Impact
Concentration, security and shared infrastructure to attract semiconductor GCCs and fabless tenants, generate high-value design jobs and exports, support startup scale-up and build recurring lease, tool and service revenues.
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